Module - 4: Sequential Logic Circuits

On completion of this module, you will be able to:

Understand what is Number Systems ?
Understand different number systems like Binary, Octal, Decimal, Hexadecimal
Understand Karnaugh Maps and their use for simplification of Boolean expressions
De-Morgan’s Theorem

Sequential Logic Circuits

The combinational circuits have set of outputs, which depends only on the present combination of inputs.
The sequential circuit is a special type of circuit that has a series of inputs and outputs. The outputs of the sequential circuits depend on both the combination of present inputs and previous outputs.
So, the sequential circuit contains the combinational circuit and its memory storage elements.
Sequential circuits are a function of both the current state and the previous state. In other words, they have memory. the block diagram of the synchronous logic circuit is shown below.

Difference between the combinational circuits and sequential circuits

S.N.	Combinational Circuits	Sequential Circuits
1	The outputs of the combinational circuit depend only on the present inputs.	The outputs of the sequential circuits depend on both present inputs and previous output.
2	The feedback path is not present in the combinational circuit.	The feedback path is present in the sequential circuits.
3	In combinational circuits, memory elements are not required.	In the sequential circuit, memory elements play an important role and require.
4	The clock signal is not required for combinational circuits.	The clock signal is required for sequential circuits.
5	The clock signal is required for sequential circuits.	The clock signal is required for sequential circuits.

Flip - Flops

A flip-flop is a sequential circuit with two stable states that can be used to store a single bit of binary data in the form of Zero (0) or (1) or we can say low or high.
So, flip-flops are storage devices that can be changed by applying varying inputs.
Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems. Both are used as data storage elements.
Latches are level sensitive and Flip-flops are edge sensitive. It means that the latch’s output change with a change in input levels and the flip-flop’s output only change when there is an edge of controlling signal. That control signal is known as a clock signal
Types of Digital Flip-Flops: Most common types of flip-flops are as follow.

SR Flip-flop
D Flip-flop
JK Flip-flop
T Flip-flop

S-R Flip - Flops

SR flip-flop is one of the most common, basic and simplest types of flip-flop. It is also known as Sr Latch.
It is a single bit storage element. It has only two logic gates. The output of each gate is connected to the input of another gate.
The state of the SR flip flop is determined by the condition of the output Q. If its value is 1, then the state is said to be SET and if its value is 0, then the state is said to be RESET. Hence it is called Set Reset(S-R) flip flop.

The logic circuit for SR Flip Flop constructed using NOR latch is as shown below which uses NOR latch and two AND gate.

The logic circuit for SR Flip Flop constructed using NAND latch is as shown below which uses NAND latch and two NAND gate.

The truth table for SR Flip Flop is as shown below-

The truth table for SR Flip Flop may be reduced as -

Characteristic Equation for SR flip flop may be written as-

The excitation table of any flip flop is drawn using its truth table. It tell us the inputs required for a given combination of present state Q_n and next state Q_n+1.

S-R Flip Flop Applications

As we know the SR Flip Flop can store 1-bit data. So we can use it in digital memory circuits.
SR Flip Flop is used in frequency divider circuits.
They are also used in digital counter circuits.

J-K Flip Flop

A JK Flip Flop simply modify version of the SR Flip Flop to ensure that the undefined state (both S and R are 1) never arises.
The inputs o an SR Flip Flp will never both be 1. So we will never have an unstable circuit.
JK means Jack Kilby, a texas instrument engineer who invented IC. A JK Flip Flop is nothing but a RS flip flop along with two AND gates which are augmented to it.
The JK Flip Flop is constructed in such a way that the output Q is ANDed with K and Clock Pulse(CP). This arrangement is made so that the flip flop is cleared during a CP only if Q was previously 1.
Similarly Q is ANDed with J and CP, so that the flip flop is cleared during a clock pulse only if Q was previously 1.

When J=K=0: when both J and K are 0, the clock pulse has no effect on the output and the output of the flip flop is same as its previous value. This is because when both the J and K are 0, the output of their respective AND gate becomes 0.
When J=1, K=0:In this case, the AND gate corresponding to K becomes 0 i.e. S=1 and R=0. Therefore Q becomes 0. This condition will set the flip flop. This represents the SET state of flip flop .
When J=K=1: when both J and K have high state, the flip flop switches to the complement state . So, when Q=1, it switches to Q=0 and for a value of Q=0, it switches to Q=1.
When J=K=0: when both J and K are 0, the clock pulse has no effect on the output and the output of the flip flop is same as its previous value. This is because when both the J and K are 0, the output of their respective AND gate becomes 0.

Excitation Table for JK Flip Flops

The excitation table of JK flip flop is the truth table of JK flip flop with additional data such as Qn as present output (current output) and Qn+1 as final output (next output).

T Flip Flop

T flip-flops are similar to JK flip -flops. T flip-flops are single input version of JK flip-flops. This modified version of JK flip-flop is obtained by connecting both inputs J and K together. This flip flop has only one input along with clock pulse.
In T flip flop, "T" defines the term "Toggle". This flip-flop work as a Toggle switch. The next output state is changed with the complement of the present state output. This process is known as "Toggling".

Operations of T-Flip Flop

The next sate of the T flip flop is similar to the current state when the T input is set to false or 0.
If toggle input is set to 0 and the present state is also 0, the next state will be 0.
If toggle input is set to 0 and the present state is 1, the next state will be 1.
The next state of the flip flop is opposite to the current state when the toggle input is set to 1.
If toggle input is set to 1 and the present state is 0, the next state will be 1.
If toggle input is set to 1 and the present state is 1, the next state will be 0.
Characteristic equation for T flip flop is shown below:.

D-Flip Flop

We connect the inverter between the Set and Reset inputs for producing another type of flip flop circuit called D flip flop, Delay flip flop, D-type Bistable, D-type flip flop..
It is basically a RS flip flop with an inverter at R input. So number of input is only one in D flip flop.
D flip flop is actually slight modification of clocked Sr flip flop. From the figure we can see that the D input is connected to S input and the complement of D input is connected to the R input.
The D input is passed on to the flip flop when the value of CP is 1 when CP is high, the flip flop moves to Set state. If it is 0 the flip flop switches to the clear state.

D Flip-flops are used as a part of memory storage elements and data processors as well. D flip-flop can be built using NAND gate or with NOR gate.
The major applications of D flip-flop are to introduce delay in timing circuit, as a buffer, sampling data at specific intervals etc.
Truth table for D flip flop isshown below.

Race Around Condition In JK Flip-flop

For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as long as CLK is high, which makes the output of the flip-flop unstable or uncertain.
This problem is called race around condition in J-K flip-flop. This problem (Race Around Condition) can be avoided by ensuring that the clock input is at logic “1” only for a very short time.
This introduced the concept of Master Slave JK flip flop.

Master-Slave JK Flip Flop

The master-slave flip-flop is designed by two JK flip-flops connected in series. The output of the first flip-flop is connected to the input of the second flip-flop.
The CLK terminals of the flip-flops are connected through a NOT gate.
When the clock pulse is high the first or master flip-flop is active and when the clock pulse is low the second or slave flip-flop is active.

Working of a master slave flip flop –

When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system.
The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0, information is passed from the master flip-flop to the slave and output is obtained.
Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so the master responds before the slave.
If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock forces the slave to reset, thus the slave copies the master.
If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition of the clock sets the slave, copying the master.
If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative transition of the clock.
If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the timing of the clock signal.

Registers

Registers are groups of flip-flop, where each flip-flop is capable of storing one bit of information. An n-bit register is a group of n flip flops.
In its broadcast definition, a register consists of a group of flip flop and gates tht effect their transition.
The basic function of a register is to hold information in a digital system and make it available to the logic elements for the computing process.
Two basic function of a register is to data storage and data movement. The shifting capability of a register permits the movement of data from stage to stage withing the register or into out of the register upon application of clock pulse.
Since each flipflop is capable of storing either 0 or a 1, there is a finite number of 0-1 combination that can be stored in a register. Each of these combination is known as state or content of the register.
A processor with 32-bit register can store 2³² different values, the same applies with 64-bit register CPU.

Registers are synchronous circuits thus all flip flops are controlled by a common clock line. As registers are often used to collect serial data they are also called accumulators.
There are maily three types of registers namely: –

Shift Registers –
Cyclic Registers –
Parallel in serial out Registers –

Shift Registers

A Register capable of shifting binary information in one or both directions is called shift register.
It consists of a series of flip-flops cascaded together with the output of one flip flop connected to the input of the other flip flop.
All flip flops receive common clock pulses that initiate the shift from one stage to the next.
They are generally provided with a Clear or Reset connection so that they can be "SET" or "RESET" as required.
Controlled with certain clock pulses by inhibiting the clock from the input of the register if shift is not required.
It is also able to provide extra circuits to control the shift operation through the D inputs of the flip flops rather than the input.

Cyclic Register or Bidirectional

A Register capable of shifting binary information in one direction only is called unidirectional shift register.
A Register that can shift in both directions is called bidirectional shift register.
Sometimes it is necessary to recycle the same values again and again. thus the bit that usually would get dropped is fed to the register input again to receive a cyclic serial register

Counters

A Register that goes through a predetermined sequence of state upon the application of input pulses is called a Counter.
A counter is a device which can count any particular event on the basis of how many times the particular event(s) is occurred.
Counters can be also defined as- It is a sequential circuits that capable of counting clock pulses. They provide accurate timing and control signals to other devices.
In a digital logic system or computers, this counter can count and store the number of time any particular event or process have occurred, depending on a clock signal.
Counting can be ascending, descending or non-linear. A counter having n-flip-flop can count upto 2ⁿ clock pulses.

A counter that follows the binary number sequence is called binary counter. The number of different states in counting sequence is also known as the Modulus of the counter.
It indicates number of states in counting sequence. If two counters are cascaded with Mod-M followed by Mod-N, then number of overall states of combined counter is (M*N) and counter is called MOD-MN counter.
If a counter counts in such a way that the decimal equivalent of the output increases with successive clock pulses,is called Up counter and if decreases, it is called Down counter
depending upon the manner in which the flip -flop are triggered, counters can be divided into two major categories -

Asynchronous counter(Ripple/series counter)
Synchronous counter(Parallel counter)

Asynchronous Counter(Ripple Counter)

For these type of counters an external clock signal is applied to one flip flop and the output of the preceding flip flop is connected to the clock of the next flip flop.
The asynchronous or ripple counter consists of series of flip-flops which are not synchronized by the same clock pulse.
Design of asynchronous counter involves several steps from selecting the number of flip-flops to drawing the logic circuit diagram.

Find the number of flip flops using 2n ≥ N, where N is the number of states and n is the number of flip flops.
Choose the type of flip flop.
Draw the truth table for asynchronous counter.
Use K-map to derive the flip flop reset input functions.
Draw the logic circuit diagram.

Design a BCD ripple counter using JK flip flops.

BCD is the 4-bit number and there are 9 valid states in a 4-bit BCD. Hence 4 flip-flops should be used in the design
The valid states are 0000, 0001, 0010,0011, 0100, 0101, 0110, 0111, 1000, 1001.
Let us design the BCD ripple / asynchronous counter with JK flip-flops.
Draw the truth table for BCD ripple counter..

The above truth table for BCD counter is implemented in a Karnaugh map to get the reset logic function.

The logic circuit diagram for BCD asynchronous/ripple counter is drawn with 4 flip-flops which is shown below.
Since it is an asynchronous counter, the clock pulse is given only to the first flip-flop.
For the other flip-flops, the output of the previous flip-flop is given as the clock pulse for the next flip-flop.
The expression obtained from the K-map is drawn using combinational circuits. The output Y is given as RESET for all the flip-flops.

Mod-4(2-bit) Synchronous up counter using J-K Flip-Flop

Synchronous Counter: In synchronous counter all the flip-flop receive the external clock pulse simultaneously. Ring counter and johnson counter are the examples of synchronous counters. In synchronous counter, the external clock applied to all the flip flop is synchronization with the circuit.
We know that n-bit synchronous counters can count N = 2ⁿ clock pulses, where n= Number of Flip-Flops. For example a 2-bit counter has 4 = 2² different states(0 to 3) and is known as the Mod - 4 counter.

The CLK inputs of all the FFs are connected together so that the input clock signal is applied to each FF simultaneously..

Shift Register Counter

Shift registers can be arranged to form different types of counters. Shift register counters uses feedback, which means the output of the last flip-flop in the register is connected back to the first flip-flop in some way.
The two commonly used shift register counters are -

Ring Counter
Johnson Counter

Ring Counter

It is the application of shift register in which output of the last flip-flop is connected to the input of first flip-flop.
Number of states in Ring counter is same as the number of flip-flop used. So for designing a 4-bit Ring counter we need 4 flip-flop.
The clock pulses(CLK) is applied to all the flip - flop simultaneously. Therefore, it is a Synchronous Counter which is shown below.

Present(PR) and Clear(CLR) are used as Overriding(ORI) for each flip flop. When PR is 0, the the output is 1 and when CLR is 0 then the output is 0.
Both PR and CLR are active low signal that always works in value 0. These two values are always fixed. They are independent of the value of input D and the clock pulse(CLK).
Working :–

Here, ORI is connected to Preset (PR) in FF-0 and it is connected to Clear (CLR) in FF-1, FF-2, and FF-3. Thus, output Q = 1 is generated at FF-0, and the rest of the flip-flop generates output Q = 0.
This output Q = 1 at FF-0 is known as Pre-set 1 which is used to form the ring in the Ring Counter.

This Preseted 1 is generated by making ORI low and that time Clock (CLK) becomes don’t care. After that ORI is made to high and apply low clock pulse signal as the Clock (CLK) is negative edge triggered.
After that, at each clock pulse, the preseted 1 is shifted to the next flip-flop and thus forms a Ring. From the above table, we can say that there are 4 states in a 4-bit Ring Counter.
four states of the Ring Counters are:
1--> 1 0 0 0
2--> 0 1 0 0
3--> 0 0 1 0
4--> 0 0 0 1
In this way we can design a 4-bit Ring Counter using four D flip-flops.
A ring counter will require more flip -flop than binary counter for the same MOD number for example MOD-8 ring counter require 8 flip-flop while a binary counter requires only 3 flip-flops.

Johnson Counter

Johnson counter is the modification of basic ring counter, where the inverted output from the last flip flop is connected to the input of the first flip-flop.
Johnson counter is also known as creeping counter, twisted ring counter, walking counter, mobile counter and switch tail counter.
The inverted output Q of the last flip-flop is connected back to the input D of the first flip-flop. The circuit diagram for a 4-bit Johnson counter is shown below:-

Johnson counter's main advantage is that it only needs half the number of flip-flops compared to the standard ring counter and then it's modulo number is halved.
So an n-stage Johnson counter will circulate a single data bit, giving a sequence of 2n different states and can therefore be considered a mod-2n counter.

If we connect five flip-flop the result is a MOD-10 Johnson counter. Thus it is possible to constuct a MOD-N counter by connecting N/2 flip-flop in Johnson counter arrangement.
Johnson counter represents a middle ground between ring counters and binary counters.
A Johnson counter requires fewer flip-flop than ring counter but more than a binary counter. It require more decoding circuit than a ring counter but less than binary counter.

Application of Counters

To count the number of Clock pulses.
To count the number of items in industry.
Work as a Frequency Divider
Used in time measurement
For distance measurement in Radar system
In Analog to Digital converter
In measurement of Pulse Repetition Interference